Differential ternary logic model with an explicit neutral equilibrium state. The project brings together Romanian and English technical papers with a software and HDL/Verilog research path. The downloadable software bundle is currently under public-scope review.
3SOS-C is presented as a mathematical and software prototype running on ordinary binary hardware. It is not claimed as a validated physical ternary processor and does not claim universal superiority over binary computation.
The ternary alphabet is {-1, 0, +1}. The central value 0 is treated as active differential equilibrium, not as absence.
The v0.8 package includes the Python core, .sos DSL, simulator, CSV/JSON export, dynamic benchmark and examples.
v0.8 adds SVG/HTML truth-table rendering, a Verilog 3SOS-C cell, a balanced ternary full-adder and a minimal testbench for future hardware exploration.
The benchmark compares a binary comparator with a ternary neutral-window model under a synthetic noisy signal. Results depend on the signal and neutral-zone parameters used in simulation.
Public technical package for the 3SOS-C branch of the Bug-Bang-Theory.org library.
PDF A5, v1.0 RC.
Deschide RO PDFA5 PDF, v1.0 RC.
Open EN PDFPython package with visual and HDL expansion.
Download ZIP