Package contents
- Python core;
- .sos DSL;
- ternary simulator;
- CSV/JSON export;
- dynamic benchmark;
- SVG/HTML/Markdown truth-table rendering;
- experimental HDL/Verilog generator.
software-first technical package
3SOS-C Software v0.8
The v0.8 package extends the 3SOS-C software prototype with visual truth-table outputs and an experimental HDL/Verilog expansion path.
v0.8 additions
output/truth_table.svg
output/truth_table.html
output/truth_table.md
output/hdl/three_sosc_cell.v
output/hdl/three_sosc_full_adder.v
output/hdl/tb_three_sosc_cell.v
output/truth_table.html
output/truth_table.md
output/hdl/three_sosc_cell.v
output/hdl/three_sosc_full_adder.v
output/hdl/tb_three_sosc_cell.v
Important limitation
The HDL layer is experimental and intended for simulation and review. It is not a validated FPGA or ASIC implementation.