Package contents
- Python core;
- .sos DSL;
- ternary simulator;
- CSV/JSON export;
- dynamic benchmark;
- SVG/HTML/Markdown truth-table rendering;
- experimental HDL/Verilog generator.
software-first technical research
3SOS-C Software v0.8
Public papers and a high-level overview remain available while the downloadable evaluation package is being reviewed and reduced.
Evaluation package under reviewRead EN paperLucrare RO
v0.8 additions
output/truth_table.svg
output/truth_table.html
output/truth_table.md
output/hdl/three_sosc_cell.v
output/hdl/three_sosc_full_adder.v
output/hdl/tb_three_sosc_cell.v
output/truth_table.html
output/truth_table.md
output/hdl/three_sosc_cell.v
output/hdl/three_sosc_full_adder.v
output/hdl/tb_three_sosc_cell.v
Important limitation
The HDL layer is experimental and intended for simulation and review. It is not a validated FPGA or ASIC implementation.